As the channel length of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) continues to shorten, a series of effects that can be neglected in the MOSFET long-channel model become more significant, and even become the dominant factor that affects performance. Such phenomenon is generally referred to as short channel effects. Short channel effects may lead to deterioration of electrical properties of devices, e.g., leading to problems such as reduction of the gate threshold voltage, increase in power consumption, and signal-to-noise ratio (SNR) decline.
In order to suppress short channel effects, the popular idea in the industry is to improve conventional planar devices, reduce the thickness of the channel region, and to eliminate the neutral layer at the bottom of the depletion layer in the channel, so that the depletion layer in the channel can fill up the entire channel region—which may be called fully depleted (Fully Depleted: FD) devices, while conventional planar devices belong to partially depleted (Partially Depleted: PD) devices.
However, the manufacture of a fully depleted device requires very thin thickness of the silicon layer in the channel. Traditional manufacturing processes, especially traditional bulk silicon-based processes can hardly manufacture structures that meet such requirements, or the cost is too high. Even for the emerging SOI (silicon on insulator) technology, the thickness of the channel silicon layer is also difficult to be controlled at a thin level. Regarding the general concept of how to achieve a fully depleted device, the focus of R & D has been shifted to 3D device structures.
3D device structures (which are also referred to as vertical-type devices in some references) refer to structures where the source/drain region of the device and the cross section of the gate are not within the same plane, and actually belong to Fin Field Effect Transistor (FinFET) structures.
After shifting to 3D device structures, since the channel region is independent from these structures rather than included in the bulk silicon or SOI, it is possible to manufacture a fully depleted channel with a very small thickness by means such as etching.
Currently, the 3D semiconductor device as shown in FIG. 16 has been proposed, and the semiconductor device comprises: a semiconductor substrate 020 located on an insulating layer 010; source/drain regions 030 connected to opposite first sides 022 in the semiconductor substrate 020; a gate 040 located on a second side 024 adjacent to the first sides 022 in the semiconductor substrate 020 (the gate dielectric layer and the work function metal layer sandwiched between the gate 040 and the semiconductor substrate 020 are not shown in the figure). In order to reduce the resistance of the source/drain region, the edge portion of the source/drain regions 030 can be extended, i.e., the width of the source/drain region 030 (along the xx′ direction) is greater than the thickness of the semiconductor substrate 020. 3D semiconductor structures are expected to be applied in the 22 nm technology node and beyond. As the scaling of device dimension, the short channel effect of 3D semiconductor devices will also become a major factor that affects the device performance.
In order to reduce the short channel effect of the device, as well as to reduce the gate leakage current, a high-k gate dielectric and metal gate process is introduced into planar devices, for example, a post-gate process is used to produce a high-k gate dielectric and metal gate. In order to suppress similar problems of the fin field effect transistor, it is required to integrate the high-k gate dielectric and metal gate process into the manufacturing process of a fin field effect transistor. Furthermore, a strained source/drain region is used in a planar device to apply stress to the channel region so as to increase the mobility of the carrier of the channel region.